A data recorder has been widely used as an external storing unit for computers and the like. As an example of the data recorder, a helical scan type data recorder that records digital data on a cassette tape as a magnetic tape with a rotating head is known. In an example of the data recorder, a magnetic recording/reproducing system of the data recorder is treated as a transmitting system corresponding to a partial response method. The recording system precodes record data. The reproducing system equalizes a signal reproduced from the head corresponding to the partial response method and identifies bits corresponding to a clock signal extracted from the signal reproduced from the head so as to reproduce data. In this method, high density data can be reproduced without errors.
FIG. 15 is a block diagram showing a recording/reproducing system of a data recorder corresponding to the partial response transmission method.
Eight-bit-word data is input. The input data has been pre-processed by an error-correction-code encoding process. In addition, a block synchronous signal has been added to the input data. The input data is supplied to an 8-to-9 converting circuit 101. The 8-to-9 converting circuit 11 converts the input data into nine-bit-word data. The resultant data is supplied as serial data to a pre-coding circuit 102. In this data recorder, the magnetic recording/reproducing system is treated as a transmitting system corresponding to a partial response (1, 0, -1) method that is known as class 4 (hereinafter, this method is referred to as PR4 method). The pre-coding circuit 102 pre-codes the input serial data into a code corresponding to the PR4 transmission method. The resultant code is the same as well known interleaved NRZI code. The pre-coded data is recorded on a magnetic tape 105 through a recording amplifier 103 and a rotating recording head 104.
The data recorded on the magnetic tape 105 is reproduced by a rotating reproducing head 106 as a reproduced data signal. The reproduced data signal is supplied to a partial response circuit 108 and a clock signal extracting circuit 109 through a reproducing amplifier 107. The reproducing amplifier 107 has a pre-filter and a cosine equalizer (not shown) that compensate the phase and frequency characteristic of the reproduced data signal so as that the frequency characteristic of the data signal reproduced from the rotating reproducing head 106 satisfies a Nyquist frequency condition. The clock signal extracting circuit 109 extracts a clock signal from the data signal reproduced from the reproducing amplifier 107. The extracted clock signal is supplied to a partial response circuit 108. The partial response circuit 108 equalizes the supplied reproduced data signal corresponding to the PR4 method, identifies bits of the equalized reproduced data signal corresponding to the clock signal supplied from the clock signal extracting circuit 109, and restores the reproduced data signal to serial data that has not been pre-coded. The restored serial data is supplied to an 8-to-9 reverse converting circuit 110. The 8-to-9 reverse converting circuit 110 converts nine-bit-word data into eight-bit-word data. Thus, the input data is restored.
In the above-described data recorder, a clock signal is extracted from the reproduced data signal. Bits are identified corresponding to the clock signal. In the clock signal extracting method, with the phased lock loop (PLL) method of which the reversing state of the polarity of the reproduced data signal is detected and the detected reversing state is used as a phase reference, a voltage control oscillator (VCO) is controlled so as to obtain a clock signal that synchronizes with the reversing state of the polarity of the reproduced data signal. FIG. 16 shows an example of the clock signal extracting circuit 109.
The clock signal extracting circuit 109 operates as follows. A reproduced data signal is supplied to an integrating circuit 91. Since the waveform of the reproduced data signal has a differential characteristic corresponding to the magnetic recording/reproducing system. The integrating circuit 91 shapes the waveform of the reproduced data signal so that the level thereof can be properly detected in the next stage. A level comparing circuit 92 digitizes the reproduced data signal that has been waveform-shaped. A phase comparing circuit 93 compares the phase of the output signal of the level comparing circuit 92 and the phase of the output signal of a voltage control oscillator 94 and controls the oscillation frequency of the voltage control oscillator 94 with an error signal obtained as the result of the comparison so that the oscillation frequency of the voltage control oscillator 94 synchronizes with the output signal of the level comparing circuit 93. Thus, the voltage control oscillator 94 outputs a clock signal that synchronizes with the reversing state of the polarity of the reproduced data signal.
However, when the clock signal extracting circuit is structured as described above, as the polarity of the reproduced data signal frequently reverses (namely, the reversing intervals of the signal polarity are short), the phase comparing operation for comparing the phase of the output signal of the level comparing circuit 92 and the phase of the output signal of the voltage control oscillator 94 increases in a predetermined time unit. Thus, the clock signal that accurately synchronizes with the reversing state of the polarity of the reproduced data signal can be effectively obtained. When the clock signal that accurately synchronizes with the reversing state of the polarity of the reproduced data signal can be obtained, bits can be accurately identified.
However, in the data recorder structured in such a manner that the recording/reproducing system is treated as a transmitting system corresponding to the partial response method, there are following problems with respect to extracting clock signal and identifying bits.
(1) Since the reversing intervals of the polarity of the data code obtained by the pre-coding circuit 102 (for example, an interleaved NRZI code) are not controlled, when the reversing intervals become very long, the reproducing system may not accurately extract the clock signal.
(2) When the clock signal cannot be accurately extracted, bits cannot be accurately identified. Thus, data cannot be correctly reproduced.
To solve such problems, in the above-described data recorder, a scrambling process and a randomizing process are performed for data to be recorded so as to artificially shorten the reversing intervals of the signal polarity.
Although the method for shortening the reversing intervals of the signal polarity as in the scrambling process and randomizing process is effective for a video signal or the like that has a correlation between adjacent data, this method is not effectively for a signal that does not have a correlation between adjacent data.